module reg_128(clk,rst,write,din,dout);

output [127:0] dout;
input  clk,write;
input rst;
input  [127:0] din;

reg [127:0] dout;

always @ (posedge clk)
begin
		if(!rst)
			dout  <= 128'h0;
		else 
		  if(write)
					 dout<=din;
		  else 
					 dout<=dout;
	end
endmodule
